When a PMOS device is subjected to different operational conditions, a shift in certain operating parameters, such as threshold voltage, can often be observed. For example, when a PMOS device is operated at a given temperature and gate bias for a given time, there tends to be a shift, or degradation, in the threshold voltage of the device. This effect is generally referred to as negative bias temperature instability. This phenomenon tends to have a large effect on analog circuit elements, such as source coupled MOSFET pairs. However, the effect tends to be transient, and the threshold voltage returns to about its original value when the charged states de-trap after the gate stress is removed.
When designing an integrated circuit, issues such as negative bias temperature instability should be accounted for, or the integrated circuit may not function properly. Certain integrated circuits, such as mixed signal cells, analog circuits, and I/O circuits may not function at all. In addition, the effects of negative bias temperature instability tend to be different for alternating current devices than they are for direct current devices.
Various experiments have been performed to measure negative bias temperature instability effects on various transistor parameters, such as voltage threshold and saturation current, at different physical conditions, such as alternating current, direct current, gate voltage, temperature, frequency, duty cycle, and stress time. Different models have been developed based upon the experimental data so produced. These models all tend to correlate a given parameter shift as a function of duty cycle, frequency, time, and temperature.
A common practice in the industry is to build the model for such parameter shifts into a larger circuit modeling routine, such as a PMOS HSPICE model library, and characterize the cell library with the negative bias temperature instability model. One drawback of this approach is that the worst case parameter is built into the model library in order to cover all possible operating conditions. Because the model is frequency and temperature dependent, this approach tends to over margin the design in most embodiments. Another drawback of this approach is that the negative bias temperature instability worst case corner—high voltage and high temperature—does not match the worst case delay corner—low voltage and high temperature. Thus, this corner-centric model library may not represent the true worst case negative bias temperature instability effect. Multiple corner libraries tend to be prohibited due to the large HSPICE simulation time required.
What is needed, therefore, is a system for including negative bias temperature instability models in integrated circuit models that overcomes problems such as those described above, at least in part.